The present invention relates generally to static random access memory (SRAM), and, more particularly, to SRAM cell array structure.
Semiconductor memory devices include, for example, static random access memory, or SRAM, and dynamic random access memory, or DRAM. DRAM memory cell has only one transistor and one capacitor, so it provides a high degree of integration. But DRAM requires constant refreshing, its power consumption and slow speed limit its use mainly for computer main memories. SRAM cell, on the other hand, is bi-stable, meaning it can maintain its state indefinitely as long as an adequate power is supplied. SRAM can operate at a higher speed and lower power dissipation, so computer cache memories use exclusively SRAMs. Other applications include embedded memories and networking equipment memories.
One well-known conventional structure of a SRAM cell is a six transistor (6T) cell that comprises six metal-oxide-semiconductor (MOS) transistors. Briefly, a 6T SRAM cell 100, as shown in FIG. 1, comprises two identical cross-coupled inverters 102 and 104 that form a latch circuit, i.e., one inverter's output connected to the other inverter's input. The latch circuit is connected between a power and a ground. Each inverter 102 or 104 comprises a NMOS pull-down transistor 115 or 125 and a PMOS pull-up transistor 110 or 120. The inverter's outputs serve as two storage nodes C and D, when one is pulled to low voltage, the other is pulled to high voltage. A complementary bit-line pair 150 and 155 is coupled to the pair of storage nodes C and D via a pair of pass-gate transistors 130 and 135, respectively. The gates of the pass-gate transistors 130 and 135 are commonly connected to a word-line 140. When the word-line voltage is switched to a system high voltage, or Vcc, the pass-gate transistors 130 and 135 are turned on to allow the storage nodes C and D to be accessible by the bit-line pair 150 and 155, respectively. When the word-line voltage is switched to a system low voltage, or Vss, the pass-gate transistors 130 and 135 are turned off and the storage nodes C and D are essentially isolated from the bit lines, although some leakage can occur. Nevertheless, as long as Vcc is maintained above a threshold, the state of the storage nodes C and D is maintained indefinitely.
Referring again to FIG. 1, during a data-hold operation, i.e., the SRAM cell 100 is neither read nor written, both bit-lines 150 and 155 are clamped to the Vcc. When writing the SRAM cell 100, one of the bit-line pair, 150 for instance, turns to a ground (Vss), while the other bit-line 155 remains at the Vcc. The Vss at the bit-line 150 will force the node C to the Vss regardless its previous state. That is to write lower voltage to the node C. If intending to write lower voltage to the node D, the bit-line 155 will swing to the Vss while the bit-line 150 remains at the Vcc. How fast the SRAM cell can be written depends on the voltage difference between the Vss and Vcc. With modern process technology shrinking transistor size as well as lowering the Vcc, the SRAM cell writing speed becomes an issue.
As such, what is desired is a SRAM cell array structure that can enhance the voltage difference between the two bit-lines during a write operation.